This invention relates to a semiconductor integrated circuit device and a manufacturing technique therefor. More particularly, the invention relates to the structure of a semiconductor integrated circuit device having DRAM (dynamic random access memory), a logic integrated circuit and the like in combination and also to a technique effective for application to the manufacture thereof.
This invention relates to a semiconductor integrate circuit device and a manufacturing technique therefor. More particularly, the invention relates to the structure of a semiconductor integrated circuit device having DRAM (dynamic random access memory), a logic integrated circuit and the like in combination and also to a technique effective for application to the manufacture thereof.
In order to realize a low resistance of a gate electrode of MISFET, there is known a technique wherein the gate electrode is made of a built-up film of a polysilicon film and a silicide film, or the gate electrode is made of a built-up film of a polysilicon film and a high melting metal such as tungsten or the like (i.e. a so-called polymetal gate).
On the other hand, for a measure of realizing a high-speed operation of a logic integrated circuit unit, there is known a technique wherein MISFET constituting a logic circuit is formed with a silicide film on the surfaces of a source and a drain thereof, respectively.
For instance, in Japanese Laid-open Patent Application No. 2000-091535 corresponding U.S. Pat. No. 6,069,038, a semiconductor integrated circuit device is stated, which makes use, as a gate electrode, of a built-up film of a polysilicon and a silicide film.
Further, in International Laid-open Application WO98/50951 corresponding U.S. patent Ser. No. 09/423,047, there is described a semiconductor integrated circuit device wherein a gate electrode is made of a built-up film of a polysilicon film and a tungsten (W) film and a silicide layer is formed on the surfaces of a source and a drain of MOSFET for a logic circuit.
We have studied and developed so-called system LSI wherein DRAM and logic LSI are formed in the same semiconductor substrate.
The DRAM formed in the system LSI has MISFET for information transmission and a capacitor element for information storage connected in series. Logic LSI has a logic circuit wherein an n channel-type MISFET and a p channel-type MISFET are appropriately combined.
Accordingly, for the formation of these elements on the same substrate, it is preferred that the MISFET for information transmission in a memory cell-forming region and the n channel-type MISFET and the p channel-type MISFET in a peripheral circuit-forming region where the logic LSI is formed are, respectively, formed according to a common process as far as circumstances permit.
In order to improve the working speed, it is required that the gate electrode of MISFET for information transmission and the gate electrodes and the sources and drains of the n channel-type MISFET and the p channel-type MISFET in the peripheral circuit-forming region be individually low in resistance. For improving the refresh characteristics of DRAM, it is also required that a leakage current between the source and drain of the MISFET for information transmission be very small.
For reducing the resistance of the gate electrode, a polycide structure may be adopted. The term xe2x80x9cpolycide gatexe2x80x9d means a technique of forming a gate electrode by patterning a built-up film of a polysilicon film and a metal silicide film.
However, this technique is disadvantageous in that the concentration of the metal in the metal silicide film cannot be made appreciably high, thus making it difficult to form a gate electrode having a sufficiently low resistance. The reason why the concentration of the metal in the metal silicide film of the polycide gate electrode cannot be made fairly high is as follows. More particularly, after the step of forming the gate electrode, the step of ion implantation for forming source and drain regions and a subsequent thermal treatment step for activating an impurity are necessary, and this, in turn, requires the adoption, as the metal polysilicide film, of a film that has a heat resistance sufficient to withstand the thermal treatment at high temperatures for the activation of the impurity. For instance, when a conductive film having a concentration of a metal higher than a stoichiometric ratio inherent to an alloy layer is formed over a polysilicon film, the metal is diffused through the high-temperature thermal treatment step, with the possibility that the semiconductor substrate is contaminated at the channel region thereof.
In the polycide gate structure, when the metal silicide film is increased in its thickness, the gate electrode can be made low in resistance. Nevertheless, in order to process a thick film, a photoresist film that is proof against the processing is necessary.
Such a thick photoresist film is poor in resolution, so that gate electrodes arranged at small intervals cannot be processed in high precision. Eventually, it becomes difficult to respond to the scale down of LSI.
Where gate electrodes constituted of a thick film are arranged at small intervals, a ratio between the interval and the height of the gate (i.e. an aspect ratio) becomes large, making it difficult to provide an insulating film or the like between the gate electrodes.
To avoid this, studies have been made on a polymetal gate structure for solving the above problem, in which a barrier metal film for preventing the diffusion of a metal and preventing a silicide reaction is interposed between a conductive film having a high metal concentration and a low resistance and a polysilicon film.
This polymetal gate structure includes, in some instance, a gate electrode constituted, for example, of a built-up film of a polysilicon film, a tungsten nitride (WN) film, and a tungsten (W) film. Aside from the tungsten nitride film, other types of metal nitrides and nitride alloys may be appropriately used as the barrier metal film. In addition, materials for use as the conductive film having a high metal concentration and a low resistance may include, aside from tungsten, other types of metals.
As stated hereinabove, for lowering a sheet resistance and a contact resistance of the source and drain regions of MISFET in the peripheral circuit region and reducing the leakage current between the source and drain of MISFET for information transmission, there is known a method wherein a silicide process is applied only to the MISFET in the peripheral circuit-forming region.
This silicide process comprises forming a metal film such as cobalt (Co), titanium (Ti) or the like on a silicon substrate, and thermally treating the film to selectively form a metal silicide layer only in a region where polysilicon or a silicon layer such as of the silicon substrate is exposed.
On the other hand, a thick etching stopper film, which is necessary for a self aligned contact (SAC) process, has to be formed on the gate electrode or side walls of the MISFET for information transmission. The etching stopper film is a film that permits an appropriate selection ratio of etching relative to an interlayer insulating film and includes, for example, an SiN film or the like.
However, where an etching stopper film is formed on the gate electrode of MISFET in the peripheral circuit-forming region along with the formation of the etching stopper film on the gate electrode or side walls of the MISFET for information transmission, it is necessary to remove the etching stopper film from the gate electrode of the MISFET in the peripheral circuit-forming region.
This is for the reason that when contact holes are made over the source and drain regions and the gate electrode of the peripheral circuit region simultaneously, the element isolation region is exposed to etching conditions over a long time, resulting in over-etching. As a result, short-circuiting takes place between a contact plug and the substrate. In order to prevent the short-circuiting, it undesirably becomes necessary to form a contact hole over the source and drain region of the peripheral circuit region and a contact hole over the gate electrode by separate steps.
However, if these contact holes are formed by separate steps, a matching allowance has to be guaranteed in the respective steps, disenabling the scale down of the element.
To avoid this, Japanese Laid-open Patent Application No. 2000-091535 proposes a method in which where a polycide gate structure is adopted, an etching stopper film on a gate electrode in a peripheral circuit-forming region has been removed beforehand.
However, when the method set out in the above application is applied to a polymetal gate structure, there has arisen the problem that a metal layer and a barrier metal layer constituting the polymetal gate are dissolved through a cleaning treatment such as with hydrofluoric acid so as to clean the substrate surface prior to the silicide process. This is a problem which occurs due to the chemical instability of a metal film constituting the polymetal gate in comparison with the metal silicide film of the polycide gate.
In this way, it is difficult that the metal film on the polymetal gate is stably left in an exposed state where the etching stopper film has been removed. Moreover, when the metal film changes in thickness, the sheet resistance of the gate electrode greatly changes, thus adversely influencing the operations of the element. Accordingly, in case where the etching stopper film has been removed from the polymetal gate in the peripheral circuit-forming region, such a semiconductor integrated circuit device and fabrication thereof as to suppress the variation in sheet resistance of the gate electrode becomes necessary.
An object of the invention is to reduce a leakage current at the source and drain regions of MISFET for information transmission and improve refresh characteristics of DRAM.
Another object of the invention is to provide a technique which is responsible for a low resistance of a gate electrode and a low resistance of a source and a drain in a peripheral circuit-forming region and also for the microfabrication of a device.
A further object of the invention is to realize the high performance and the high degree of integration of a DRAM unit and a logic LSI unit.
These and other objects and novel features of the invention will become apparent from the description of the specification with reference to the accompanying drawings.
Typical embodiments of the invention are briefly described below.
1. The semiconductor integrated circuit device of the invention is arranged such that a gate electrode of MISFET for information transmission in a memory cell-forming region has a metal layer, and gate electrodes of n channel-type MISFET and p channel-type MISFET in a peripheral circuit-forming region, respectively, have a first metal silicide layer wherein these MISFET""s, respectively, have a second metal silicide layer formed on a source and a drain thereof. According to this arrangement, the gate electrode of the MISFET for information transmission can be made low in resistance. Moreover, the gate electrodes of the n channel and p channel-type MISFET""s in the peripheral circuit-forming region can be made low in resistance, and the source and drain thereof can also be made low in resistance.
Further, because no metal silicide layer is formed on the source and drain of the MISFET for formation transmission, it is expected to improve refresh characteristics owing to the reduction of a leakage current.
The gate electrode of the MISFET for information transmission is formed of a built-up film of a silicon layer and a metal layer formed thereon. The gate electrodes of the n channel-type MISFET and p channel-type MISFET in the peripheral circuit-forming region are, respectively, made of a silicon layer and a metal silicide layer formed thereon. The metal silicide includes, for example, cobalt or titanium silicide. The metal silicide layer is formed by silification reaction.
A buried conductive layer may be formed on the gate electrode of the n channel-type MISFET or p channel-type MISFET in the peripheral circuit-forming region. In this way, no protective layer is formed over the gate electrode of the n channel-type MISFET or p channel-type MISFET, and thus, a contact hole in which a buried conductive layer is formed can be precisely formed.
2. The semiconductor integrated circuit device of the invention is arranged such that a gate electrode of MISFET for information transmission in a memory cell-forming region has a metal layer, and gate electrodes of n channel-type MISFET and p channel-type MISFET constituting SRAM memory cell in a peripheral circuit-forming region, respectively, have a first metal silicide layer wherein these MISFET""s, respectively, have a second metal silicide layer formed on a source and a drain thereof. According to this arrangement, the gate electrode of the MISFET for information transmission can be made low in resistance. Moreover, the gate electrodes of the n channel and p channel-type MISFET""s constituting SRAM can be made low in resistance, and the source and drain thereof can also be made low in resistance.
Because any metal silicide layer is formed on the source and drain of the MISFET for information transmission, it is possible to improve refresh characteristics owing to the reduction in leakage current.
The gate electrode of the MISFET for information transmission is formed of a built-up film of a silicon layer and a metal layer formed thereon. The gate electrodes of the n channel-type MISFET and the p channel-type MISFET for SRAM are, respectively, formed of a silicon layer and a metal silicide layer formed thereon. The metal layer is made, for example, of tungsten. The metal silicide includes, for example, cobalt or titanium silicide. The metal silicide layer is formed by silification reaction.
A buried conductive layer may be formed over the gate electrode of the n channel-type MISFET or the p channel-type MISFET constituting SRAM. In this way, no protective layer is formed over the gate electrode of the n channel-type MISFET or p channel-type MISFET, and thus, a contact hole in which a buried conductive layer is formed can be precisely formed.
3. A method for fabricating a semiconductor integrated circuit device according to the invention comprises the steps of successively forming a polysilicon film and a high melting metal film on a gate insulating film and patterning the films to form a gate electrode in a memory cell-forming region and a peripheral circuit-forming region, respectively, removing the high melting metal film from the gate electrode in the peripheral circuit-forming region, and depositing a metal layer over the peripheral circuit-forming region, followed by thermal treatment to form a silicide film on the polysilicon film and a high concentration diffusion layer in the gate electrode of the peripheral circuit-forming region. According to this method, there can be obtained a semiconductor integrated circuit device having a high performance and a high degree of integration. Moreover, in case where a contact hole is formed over the silicide film on the polysilicon film of the peripheral circuit-forming region in a subsequent step, the silicide film has no protective film, so that the contact hole can be formed in high precision.
4. The above method can be applied to the fabrication of a semiconductor integrated circuit device having an n channel-type MISFET and a p channel-type MISFET constituting SRAM formed in a peripheral circuit-forming region.